1. Field of Invention
The invention relates generally to phase locked loops, particularly to the elimination of dead zone for phase locked loops using binary quantized phase detectors.
2. Description of Related Art
Clock recovery circuits (CRC) are often used in communication systems and other electronic systems to synchronize a local clock to an external system clock. Currently, a phase locked loop (PLL) is the standard approach to constructing a CRC.
FIG. 1 shows a conventional phase locked loop, including the basic components: a phase and frequency detector denoted 1, a low pass filter (LPF) denoted 3, and a voltage-controlled oscillator (VCO) denoted 5.
The phase and frequency detector 1 compares a reference signal denoted 7 to a feedback signal denoted 11 in order to produce a phase error signal denoted 9. The phase error signal 9 is then filtered through the low pass filter 3 and subsequently input to the VCO 5. The VCO 5 generates a signal 11 with a frequency controlled by the filtered phase error signal. The output 11 is fed back into the phase and frequency detector 1. If the two frequencies for the signals 7 and 11 do not equal, the filtered phase error signal would cause the VCO 5 to shift to the frequency of the reference signal 7. When the shift is completed, the output of the VCO 5 is used as the synchronized signal.
Several types of phase locked loops have been developed using phase detectors such as Alexander phase detector and Hogge phase detector. Particularly, the Alexander phase detector has been widely adopted due to its ease of implementation.
A CRC measures the clock phase and aligns it to the reference clock to minimize bit-error-rate, and the optimum sampling instant is at the center of the data-eye. FIG. 2 illustrates a data-eye diagram with two data-eyes having centers denoted 17 and 19 and a cross point denoted 13. An Alexander phase detector uses the cross point 13 sample as a reference to locate the data-eye centers.
However, due to duty cycle distortion, the cross point 13 in FIG. 2 is offset from the threshold 0 by a dead zone denoted 15. The duty-cycle distortion causes an Alexander phase detector to wander in the interval denoted 14, searching for the cross point, thereby offsetting the locations of the data-eye centers 17 and 19.